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1 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer may 2010 2010 integrated device technology, inc. dsc 6994/5 c commercial and industrial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. features: ? phase-lock loop clock distribution ? 10mhz to 133mhz operating frequency ? distributes one clock input to one bank of five outputs ? zero input-output delay ? output skew < 250ps ? low jitter <175 ps cycle-to-cycle ? 50ps typical cycle-to-cycle jitter (15pf, 66mhz) ? idt2305b-1 for standard drive ? idt2305b-1h for high drive ? no external rc network required ? operates at 3.3v v dd ? power down mode ? available in soic and tssop packages functional block diagram idt2305b 3.3v zero delay clock buffer description: the idt2305b is a high-speed phase-lock loop (pll) clock buffer, designed to address high-speed clock distribution applications. the zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133mhz. the idt2305b is an 8-pin version of the idt2309b. idt2305b accepts one reference input, and drives out five low skew clocks. the -1h version of this device operates, up to 133mhz frequency and has a higher drive than the -1 device. all parts have on-chip plls which lock to an input clock on the ref pin. the pll feedback is on-chip and is obtained from the clkout pad. in the absence of an input clock, the idt2305b enters power down. in this mode, the device will draw less than 25 a, the outputs are tri-stated, and the pll is not running, resulting in a significant reduction of power. the idt2305b is characterized for both industrial and commercial operation. pll 8 clk1 clk2 clk3 clk4 control logic ref clkout 1 3 2 5 7
2 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer pin configuration soic/tssop top view symbol rating max. unit v dd supply voltage range ?0.5 to +4.6 v v i (2) input voltage range (ref) ?0.5 to +5.5 v v i input voltage range ?0.5 to v (except ref) v dd +0.5 i ik (v i < 0) input clamp current ?50 ma i o (v o = 0 to v dd ) continuous output current 50 ma v dd or gnd continuous current 100 ma t a = 55c maximum power dissipation 0.7 w (in still air) (3) t stg storage temperature range ?65 to +150 c operating commercial temperature 0 to +70 c temperature range operating industrial temperature -40 to +85 c temperature range notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. the maximum package power dissipation is calculated using a junction temperature of 150c and a board trace length of 750 mils. notes: 1. weak pull down. 2. weak pull down on all outputs. pin description absolute maximum ratings (1) applications: ? sdram ? telecom ? datacom ? pc motherboards/workstations ? critical path delay designs pin name pin number type functional description ref (1) 1 in input reference clock, 5 volt tolerant input clk2 (2) 2 out output clock clk1 (2) 3 out output clock gnd 4 ground ground clk3 (2) 5 out output clock v dd 6 pwr 3.3v supply clk4 (2) 7 out output clock clkout (2) 8 out output clock, internal feedback on this pin ref clk1 2 3 4 8 7 6 5 1 clk2 gnd clkout clk4 v dd clk3
3 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer symbol parameter min. max. unit v dd supply voltage 3 3.6 v t a operating temperature (ambient temperature) 0 70 c c l load capacitance < 100mhz ? 30 pf load capacitance 100mhz - 133mhz ? 10 c in input capacitance ? 7 pf operating conditions - commercial dc electrical characteristics - commercial symbol parameter conditions min. max. unit v il input low voltage level ? 0.8 v v ih input high voltage level 2 ? v i il input low current v in = 0v ? 50 a i ih input high current v in = v dd ? 100 a v ol output low voltage standard drive i ol = 8ma ? 0.4 v high drive i ol = 12ma (-1h) v oh output high voltage standard drive i oh = -8ma 2.4 ? v high drive i oh = -12ma (-1h) i dd_pd power down current ref = 0mhz ? 12 a i dd supply current unloaded outputs at 66.66mhz ? 32 ma switching characteristics (2305b-1) - commercial (1,2) symbol parameter conditions min. typ. max. unit t 1 output frequency 10pf load 10 ? 133 mhz 30pf load 10 ? 100 duty cycle = t 2 t 1 measured at 1.4v, f out = 66.66mhz 40 50 60 % t 3 rise time measured between 0.8v and 2v ? ? 2.5 ns t 4 fall time measured between 0.8v and 2v ? ? 2.5 ns t 5 output to output skew all outputs equally loaded ? ? 250 ps t 6 delay, ref rising edge to clkout rising edge measured at v dd /2 ? 0 350 ps t 7 device-to-device skew measured at v dd /2 on the clkout pins of devices ? 0 700 ps t j cycle-to-cycle jitter measured at 66.66mhz, loaded outputs ? 50 175 ps t lock pll lock time stable power supply, valid clock presented on ref pin ? ? 1 ms notes: 1. ref input has a threshold voltage of v dd /2. 2. all parameters specified with loaded outputs.
4 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer symbol parameter min. max. unit v dd supply voltage 3 3.6 v t a operating temperature (ambient temperature) -40 +85 c c l load capacitance < 100mhz ? 30 pf load capacitance 100mhz - 133mhz ? 10 c in input capacitance ? 7 pf operating conditions - industrial switching characteristics (2305b-1h) - commercial (1,2) symbol parameter conditions min. typ. max. unit t 1 output frequency 10pf load 10 ? 133 mhz 30pf load 10 ? 100 duty cycle = t 2 t 1 measured at 1.4v, f out = 66.66mhz 40 50 60 % duty cycle = t 2 t 1 measured at 1.4v, f out <50mhz 45 50 55 % t 3 rise time measured between 0.8v and 2v ? ? 1.5 ns t 4 fall time measured between 0.8v and 2v ? ? 1.5 ns t 5 output to output skew all outputs equally loaded ? ? 250 ps t 6 delay, ref rising edge to clkout rising edge measured at v dd /2 ? 0 350 ps t 7 device-to-device skew measured at v dd /2 on the clkout pins of devices ? 0 700 ps t 8 output slew rate measured between 0.8v and 2v using test circuit #2 1 ? ? v/ns t j cycle-to-cycle jitter measured at 66.66mhz, loaded outputs ? ? 175 ps t lock pll lock time stable power supply, valid clock presented on ref pin ? ? 1 ms notes: 1. ref input has a threshold voltage of v dd /2. 2. all parameters specified with loaded outputs. dc electrical characteristics - industrial symbol parameter conditions min. max. unit v il input low voltage level ? 0.8 v v ih input high voltage level 2 ? v i il input low current v in = 0v ? 50 a i ih input high current v in = v dd ? 100 a v ol output low voltage standard drive i ol = 8ma ? 0.4 v high drive i ol = 12ma (-1h) v oh output high voltage standard drive i oh = -8ma 2.4 ? v high drive i oh = -12ma (-1h) i dd_pd power down current ref = 0mhz ? 25 a i dd supply current unloaded outputs at 66.66mhz ? 35 ma
5 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer switching characteristics (2305b-1h) - industrial (1,2) symbol parameter conditions min. typ. max. unit t 1 output frequency 10pf load 10 ? 133 mhz 30pf load 10 ? 100 duty cycle = t 2 t 1 measured at 1.4v, f out = 66.66mhz 40 50 60 % duty cycle = t 2 t 1 measured at 1.4v, f out <50mhz 45 50 55 % t 3 rise time measured between 0.8v and 2v ? ? 1.5 ns t 4 fall time measured between 0.8v and 2v ? ? 1.5 ns t 5 output to output skew all outputs equally loaded ? ? 250 ps t 6 delay, ref rising edge to clkout rising edge measured at v dd /2 ? 0 350 ps t 7 device-to-device skew measured at v dd /2 on the clkout pins of devices ? 0 700 ps t 8 output slew rate measured between 0.8v and 2v using test circuit #2 1 ? ? v/ns t j cycle-to-cycle jitter measured at 66.66mhz, loaded outputs ? ? 175 ps t lock pll lock time stable power supply, valid clock presented on ref pin ? ? 1 ms notes: 1. ref input has a threshold voltage of v dd /2. 2. all parameters specified with loaded outputs. switching characteristics (2305b-1) - industrial (1,2) symbol parameter conditions min. typ. max. unit t 1 output frequency 10pf load 10 ? 133 mhz 30pf load 10 ? 100 duty cycle = t 2 t 1 measured at 1.4v, f out = 66.66mhz 40 50 60 % t 3 rise time measured between 0.8v and 2v ? ? 2.5 ns t 4 fall time measured between 0.8v and 2v ? ? 2.5 ns t 5 output to output skew all outputs equally loaded ? ? 250 ps t 6 delay, ref rising edge to clkout rising edge measured at v dd /2 ? 0 350 ps t 7 device-to-device skew measured at v dd /2 on the clkout pins of devices ? 0 700 ps t j cycle-to-cycle jitter measured at 66.66mhz, loaded outputs ? 50 175 ps t lock pll lock time stable power supply, valid clock presented on ref pin ? ? 1 ms notes: 1. ref input has a threshold voltage of v dd /2. 2. all parameters specified with loaded outputs.
6 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer ref to clka/clkb delay (ps) zero delay and skew control all outputs should be uniformly loaded in order to achieve zero i/o delay. since the clkout pin is the internal feedback for th e pll, its relative loading can affect and adjust the input/output delay. the output load difference diagram illustrates the pll's relative loading with respect to the other outputs that can adjust the input-output (i/o) delay. for designs utilizing zero i/o delay, all outputs including clkout must be equally loaded. even if the output is not used, it m ust have a capacitive load equal to that on the other outputs in order to obtain true zero i/o delay. if i/o delay adjustments are needed, use the o utput load difference diagram to calculate loading differences between the clkout pin and other outputs. for zero output-to-output skew, all outputs must be loaded equally. ref to clka/clkb relay vs. output load difference between clkout pin and clka/clkb pins output load difference between clkout pin and clka/clkb pins (pf)
7 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer all outputs rise/fall time input to output propagation delay device to device skew output to output skew duty cycle timing switching waveforms test circuit 1 (all parameters except t8) test circuit 2 (t8, output slew rate on -1h devices) test circuits v dd outputs v dd gnd gnd 0.1 f 0.1 f v dd outputs 10pf v dd gnd gnd 0.1 f 0.1 f 1k 1k c load clk out clk out output 1.4v 1.4v t5 output ref v dd/ 2 t6 output clk out device 1 t7 clk out device 2 v dd/ 2 v dd /2 v dd /2 1.4v 1.4v t2 t1 1.4v 2v 0.8v t3 t4 0.8v 3.3v 0v 2v output
8 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer typical duty cycle (1) and i dd trends (2) for idt2305b-1 notes: 1. duty cycle is taken from typical chip measured at 1.4v. 2. i dd data is calculated from i dd = i core + ncvf, where i core is the unloaded current. (n = number of outputs; c = capacitance load per output (f); v = supply voltage (v); f = frequency (hz)) 3 3.1 3.2 3.3 3.4 3.5 3.6 v dd (v) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs v dd (for 30pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz d u t y c y c l e ( % ) 3 3.1 3.2 3.3 3.4 3.5 3.6 v dd (v) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs v dd (for 10pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz 20 40 60 80 100 120 140 frequency (mhz) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs frequency (for 30pf loads over temperature - 3.3v) -40c 0c 25c 70c 85c d u t y c y c l e ( % ) d u t y c y c l e ( % ) 133mhz 20 40 60 80 100 120 140 frequency (mhz) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs frequency (for 10pf loads over temperature - 3.3v) -40c 0c 25c 70c 85c d u t y c y c l e ( % ) 02 4 6 8 number of loaded outputs 0 20 40 60 80 100 120 140 i dd vs number of loaded outputs (for 30pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz i d d ( m a ) 02 4 6 8 number of loaded outputs 0 20 40 60 80 100 120 140 i dd vs number of loaded outputs (for 10pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz i d d ( m a )
9 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer typical duty cycle (1) and i dd trends (2) for idt2305b-1h notes: 1. duty cycle is taken from typical chip measured at 1.4v. 2. i dd data is calculated from idd = icore + ncvf, where icore is the unloaded current. (n = number of outputs; c = capacitance load per output (f); v = supply voltage (v); f = frequency (hz)) 3 3.1 3.2 3.3 3.4 3.5 3.6 v dd (v) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs v dd (for 30pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz d u t y c y c l e ( % ) 3 3.1 3.2 3.3 3.4 3.5 3.6 v dd (v) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs v dd (for 10pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz 20 40 60 80 100 120 140 frequency (mhz) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs frequency (for 30pf loads over temperature - 3.3v) -40c 0c 25c 70c 85c d u t y c y c l e ( % ) d u t y c y c l e ( % ) 133mhz 20 40 60 80 100 120 140 frequency (mhz) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs frequency (for 10pf loads over temperature - 3.3v) -40c 0c 25c 70c 85c d u t y c y c l e ( % ) 02 4 6 8 number of loaded outputs 0 20 40 60 80 100 120 140 i dd vs number of loaded outputs (for 30pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz i d d ( m a ) 02 4 6 8 number of loaded outputs 0 20 40 60 80 100 120 140 i dd vs number of loaded outputs (for 10pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz i d d ( m a ) 160 160
10 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer 150 mil (narrow body) soic seating plane seating plane a1 b a e .10 (.004) .10 (.004) h x 45 h x 45 min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d e 3.80 4.00 .1497 .1574 e h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 n 0 8 0 8 variations min max min max 8 4.80 5.00 .1890 .1968 10-0030 0.050 basic symbol in millimeters in inches common dimensions common dimensions reference doc.: jedec publication 95, ms-012 150 mil (narrow body) soic see variations see variations n d mm. d (inch) see variations see variations 1.27 basic 8-pin soic package drawing and dimensions
11 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer index area index area 12 1 2 n d e1 e e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n a 0808 aaa -- 0.10 -- .004 variations min max min max 8 2.90 3.10 .114 .122 10-0035 see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol 8-pin tssop package drawing and dimensions
12 commercial and industrial temperature ranges idt2305b 3.3v zero delay clock buffer ordering information corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 clockhelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com idt xxxxx xx x package process device type 2305b-1 2305b-1h zero delay clock buffer high drive output dc dcg small outline soic - green blank i commercial (0 o cto+70 o c) industrial (-40 o cto+85 o c) pgg tssop - green ordering code package type operating range 2305b-1dcg8 (tape and reel) 8-pin soic commercial 2305b-1dcg 8-pin soic commercial 2305B-1HDCG8 (tape and reel) 8-pin soic commercial 2305b-1hdcg 8-pin soic commercial 2305b-1hdcgi8 (tape and reel) 8-pin soic industrial 2305b-1hdcgi 8-pin soic industrial 2305b-1pgg 8-pin tssop commercial 2305b-1pgg8 (tape and reel) 8-pin tssop commercial 2305b-1pggi 8-pin tssop industrial 2305b-1pggi8 (tape and reel) 8-pin tssop industrial

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